Posts for si-list, 10-2003

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  1. » [SI-LIST] Compact PCI backplane overshoot/undershoot diode array, Nico Fleurinck
  2. » [SI-LIST] Antwort: Simulating Wiring Harnesses and Cables., Dirk Eyfrig
  3. » [SI-LIST] Ansoft Global Seminars, Brad Cole
  4. » [SI-LIST] Re: Hardware Design guru - FYI, Ken Cantrell
  5. » [SI-LIST] SREC utility, Adeel Malik
  6. » [SI-LIST] On choosing center tap capacitor value for differential termination, Tom Cipollone
  7. » [SI-LIST] Re: On choosing center tap capacitor value for differential termination, Mirmak, Michael
  8. » [SI-LIST] Re: Off topic -- Electrical Component Abbreviations, Mirmak, Michael
  9. » [SI-LIST] UltraCAD's calculator bug update, Doug Brooks
  10. » [SI-LIST] Re: USB 2.0 testing, Tadashi Arai
  11. » [SI-LIST] Re: HyperLynx vs Hspice, Ekkehard Miersch
  12. » [SI-LIST] Diff.Pairs, Juergen Flamm
  13. » [SI-LIST] negative propagation delay, Perry Qu
  14. » [SI-LIST] Re: negative propagation delay, Lai, Ricky (Eng Hou)
  15. » [SI-LIST] Re: Guard traces for differential pairs, Duane Takahashi
  16. » [SI-LIST] Congratulations on a needed book, MikonCons
  17. » [SI-LIST] A question about reference plane in gigabit ethernet design!, Jack W.C. Lin
  18. » [SI-LIST] Re: power consuming of OSC, Bi Han
  19. » [SI-LIST] Fwd: Re: High Impedance Traces are prone to Radio Frequency Interference, Bi Han
  20. » [SI-LIST] Re: A question about reference plane in gigabit ethernet design!, Loyer, Jeff
  21. » [SI-LIST] ESD Issues, Steve Mitchell
  22. » [SI-LIST] Re: ESD Issues, Salkow, Steven
  23. » [SI-LIST] IBIS Interconnect Modeling (ICM) Specification 1.0 now available, Mirmak, Michael
  24. » [SI-LIST] Re: Diff.Pairs, Lee Ritchey
  25. » [SI-LIST] Re: Diff. Pairs, Ravinder . Ajmani
  26. » [SI-LIST] Re: [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition], Muranyi, Arpad
  27. » [SI-LIST] Re: Diff Pairs, Scott McMorrow
  28. » [SI-LIST] Re: BBC Presentation--James Clark Maxwell, Abdulrahman Rafiq
  29. » [SI-LIST] Re: HSPICE - Deciding Max. route length, Bi Han
  30. » [SI-LIST] Looking for Job, Maeda
  31. » [SI-LIST] Impedance Uniformity, Mike Kauffman
  32. » [SI-LIST] Heisenberg and signal measurements, Doug Smith
  33. » [SI-LIST] Diff. Pairs, Eric Bogatin
  34. » [SI-LIST] implemented peeling algorithm for TDR, pendayal
  35. » [SI-LIST] Antenna currents and digital Ground, davidpauljones2003
  36. » [SI-LIST] Very Basic question, Haritha Chanda
  37. » [SI-LIST] Re: Antenna currents and digital Ground, Salkow, Steven
  38. » [SI-LIST] FW: Diff. Pairs, Paul Ikeda
  39. » [SI-LIST] operational amplifiers, Zhangkun
  40. » [SI-LIST] AD9901, Felix Recht
  41. » [SI-LIST] magnetic permeability in dielectric loss, jojo
  42. » [SI-LIST] call for papers, Igor Balk
  43. » [SI-LIST] magnetic permeability, jojo
  44. » [SI-LIST] Re: rf boards, David Kaiser
  45. » [SI-LIST] Re: operational amplifiers, Juergen Flamm
  46. » [SI-LIST] TRANSISTORS ?, Steve Rogers
  47. » [SI-LIST] Re: Hardware Design guru - FYI, David Cohen
  48. » [SI-LIST] How to use common mode chock to elimate Common-mode noise ?, ªü¥È
  49. » [SI-LIST] Re: Capacitors and Anti-resonance, Lee Ritchey
  50. » [SI-LIST] OrCAD to Concept HDL Schematics conversions, Vishnu Jwalapuram Jwala
  51. » [SI-LIST] Couple of Questions for a starter, sale sale
  52. » [SI-LIST] Re: Heisenberg and signal measurements, Zhou, Xingling (Mick)
  53. » [SI-LIST] unsubscribe, amrita sahoo
  54. » [SI-LIST] DDR2- 800MBPS timing requirements, John Ellis
  55. » [SI-LIST] PS decoupling for QFP and similars, Chacon Simon, Geoffrey
  56. » [SI-LIST] Traces don't cause EMI - really?, Grasso, Charles
  57. » [SI-LIST] Re: PS decoupling for QFP and similars, Mangipudi, Prasad
  58. » [SI-LIST] Papers - a little help, please, Bob Perlman
  59. » [SI-LIST] Re: Papers - a little help, please, Grasso, Charles
  60. » [SI-LIST] Single ended via analysis, Scott McMorrow
  61. » [SI-LIST] RMCEMC September Meeting slides available for download, Charles Grasso
  62. » [SI-LIST] Re: Traces don't cause EMI - really?, Lee Ritchey
  63. » [SI-LIST] XTK issue, BRanjul
  64. » [SI-LIST] Specs. of a double-sided PCI board, shaymaa nabil
  65. » [SI-LIST] Attenuation in Lumped and Disstributed model, Haritha Chanda
  66. » [SI-LIST] Re: Traces don't cause EMI - really?...and Diff. pairs, Clewell, Craig
  67. » [SI-LIST] Re: Attenuation in Lumped and Disstributed model, MikonCons
  68. » [SI-LIST] SI Job Opportunity at Extreme Networks - Req # 751, Nitin Bhandari
  69. » [SI-LIST] Emi from traces - paper eference, Charles Grasso
  70. » [SI-LIST] ESD protection devices, Nigel Hughes
  71. » [SI-LIST] Re: ESD protection devices, Geoff Stokes
  72. » [SI-LIST] VCCINT 1.2 Vlot For Spartan3 Device, anshul
  73. » [SI-LIST] PCI and PCI-X bus noise, swldstn
  74. » [SI-LIST] modeling and simulating transmission line, Harish K Subramanian
  75. » [SI-LIST] How to build a variable resistor in HSPICE, David Kaiser
  76. » [SI-LIST] Re: How to build a variable resistor in HSPICE, Beal, Weston
  77. » [SI-LIST] Hspice differential Tline, timoceous
  78. » [SI-LIST] Re: Hspice differential Tline, Raymond . Leung
  79. » [SI-LIST] ESD through Ferrite core, BRanjul
  80. » [SI-LIST] need of voltage regulator for SPARTAN-III VCCINT supply, anshul
  81. » [SI-LIST] TIME TO VM question!, Jack W.C. Lin
  82. » [SI-LIST] LNAs, Kella Vijay Chander
  83. » [SI-LIST] Re: PCI and PCI-X bus noise, Gregory R Edlund
  84. » [SI-LIST] Terrmination techniques in SoCs ???, manthos labropoulos
  85. » [SI-LIST] FYI: "Right By Design" Seminar, Kathy Breda
  86. » [SI-LIST] permeabilty, atifshamim khan
  87. » [SI-LIST] Re: Diff.Pairs - Return current distribution, Knighten, Jim L
  88. » [SI-LIST] PCI and PCI-X Bus Noise Followup, swldstn
  89. » [SI-LIST] Re: TIME TO VM question!, Jack W.C. Lin
  90. » [SI-LIST] where can I get a free eval HSPICE or portion of it?, Hong Shi
  91. » [SI-LIST] circuit simulations, Doug Smith
  92. » [SI-LIST] Re: ESD through Ferrite core, BRanjul
  93. » [SI-LIST] 50ohm SSTL2 Tx, Rajat Chauhan
  94. » [SI-LIST] Re: circuit simulations, Geoff Stokes
  95. » [SI-LIST] Need Information On Limiting Amplifier Design, Balasubramaniam Shammugasamy
  96. » [SI-LIST] How to set I/O pins to high-Z state, Gian YK-r58635
  97. » [SI-LIST] about ethernet phy interface question, qzheng
  98. » [SI-LIST] ESD wire, BRanjul
  99. » [SI-LIST] Diff Impedance and its noise immunity., ªü¥È
  100. » [SI-LIST] Re: Traces don't cause EMI - really?--oops, MikonCons
  101. » [SI-LIST] Re: Active components on a highspeed backplane, Dimiter Popoff
  102. » [SI-LIST] RLGC Parameters, group_delay
  103. » [SI-LIST] Re: si-list: winbery@comcast.net post needs approval, Raymond Anderson
  104. » [SI-LIST] How to import hspice into ADS, shemshak
  105. » [SI-LIST] s-parameter citi file format, Mei Luo
  106. » [SI-LIST] A question, amar mysore
  107. » [SI-LIST] Re: s-parameter citi file format, Bart Bouma
  108. » [SI-LIST] Re: Diff Impedance and its noise immunity., Geoff Stokes
  109. » [SI-LIST] PCI-X/PCI Ground/Power Voltage Drop, Steven M. Waldstein
  110. » [SI-LIST] Re: RLGC Parameters, Clewell, Craig
  111. » [SI-LIST] SerDes vs. PHY for Gigabit Ethernet, David Shapiro
  112. » [SI-LIST] Re: SerDes vs. PHY for Gigabit Ethernet, Massimo . Panonzini
  113. » [SI-LIST] Crystal Oscillator design, 郭 亚炜
  114. » [SI-LIST] Re: si-list Digest V3 #305, Steffen Hagene
  115. » [SI-LIST] Re: A question, Abe Riazi
  116. » [SI-LIST] Modelling semiconductors in 2D field solvers, Anil Pannikkat
  117. » [SI-LIST] Re: LNAs, D G
  118. » [SI-LIST] Signal Integrity Seminar October 24, San Jose, Tom Flynn
  119. » [SI-LIST] EMC Society papers available on CD-ROM, Charles Grasso
  120. » [SI-LIST] KPn and KPp in Level 49 spice transistor model, manthos labropoulos
  121. » [SI-LIST] Help to see the DDR differential clock waveform in PCB, hai tian
  122. » [SI-LIST] how to use star_rcxt to extract spf ?, Michael Zeng
  123. » [SI-LIST] Re: Paper reference to download, Grasso, Charles
  124. » [SI-LIST] LINPAR dos user-defined structure, jihong ren
  125. » [SI-LIST] PCB Radiated Emissions paper available for download, Charles Grasso
  126. » [SI-LIST] What are the differencs between W, T and U-element of a tranmission line model?, lee yang
  127. » [SI-LIST] What's the reason for the following layout rule?, Allen_Wang
  128. » [SI-LIST] Please unsubscribe, Bob Hays
  129. » [SI-LIST] How to compile netlist in DRACUlA, Michael Zeng
  130. » [SI-LIST] A couple comments on list etiquette and respect for others opinions, Raymond Anderson
  131. » [SI-LIST] Rigid-Flex Testing, Jackson, T L
  132. » [SI-LIST] Re: Rigid-Flex Testing, Clewell, Craig
  133. » [SI-LIST] ERROR CALCULATIONS, Moeller, Merrick
  134. » [SI-LIST] Differential Signalling through Tri-axial Cable ?...., Comiskey, Peter
  135. » [SI-LIST] REMINDER Oct 27 & 28 - NESA Seminar: "Signal Integrity Principles for Gigabit Connector, Cable and Semiconductor Package Designs", Kathy Breda
  136. » [SI-LIST] Ethernet simulations, Painter, Chris
  137. » [SI-LIST] Re: Ethernet simulations, Michael Poimboeuf
  138. » [SI-LIST] Power plane frequency range and noise level, =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  139. » [SI-LIST] Why crosstalk calculation does not count into trace width?, Allen_Wang
  140. » [SI-LIST] Re: Power plane frequency range and noise level, =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
  141. » [SI-LIST] SI impact on BGA Ball placement and pwr/gnd ratios, swldstn
  142. » [SI-LIST] 3.125Gpbs Based backplane solutions, Harjeet Singh Randhawa, Noida
  143. » [SI-LIST] Re: Differential Signalling through Tri-axial Cable ?...., MikonCons
  144. » [SI-LIST] Lee - Paper avaiable on RMCEMC website., Grasso, Charles
  145. » [SI-LIST] Re: SI impact on BGA Ball placement and pwr/gnd ratios, Anil Pannikkat
  146. » [SI-LIST] Re: KPn and KPp in Level 49 spice transistor model, Hari krishnan
  147. » [SI-LIST] Re: Why crosstalk calculation does not count into trace width?, =?big5?b?IkhvLCBKZWZmICim86xGvrEgSUVDMSki?=
  148. » [SI-LIST] SPI -4 interface, Sudheer B S
  149. » [SI-LIST] SSTL2 class-II twice or thrice of Class-I, raj singh
  150. » [SI-LIST] TDR VTT Question, Paul Levin
  151. » [SI-LIST] Re: What are the differencs between W, T and U-element of atranmission line model?, lee yang
  152. » [SI-LIST], Ravinder . Ajmani
  153. » [SI-LIST] Sacrificial ground: Is it useful?, John Coupland
  154. » [SI-LIST] SI contract opportunity in California, Kevin Pierpoint
  155. » [SI-LIST] BiTS Burn-in & Test Socket Workshop - Call For Presentations abstract submission deadline extension, Treibergs, Valts
  156. » [SI-LIST] Re: SI contract opportunity in California, Youssef Khalife
  157. » [SI-LIST] Components Assembly Cost, Adeel Malik
  158. » [SI-LIST] Complex voltage division in Hspice?, A.Z.
  159. » [SI-LIST] Re: Complex voltage division in Hspice?, Guo Yawei
  160. » [SI-LIST] Re: Sacrificial ground: Is it useful?, MikonCons
  161. » [SI-LIST] testing, A.Z.
  162. » [SI-LIST] Field-solver, elecqs
  163. » [SI-LIST] About the limit of minimum length, "Fu, Greg (付?操 IES)"
  164. » [SI-LIST] Re: What are the differences between W, T and U-element of a transmission line model?, Clewell, Craig
  165. » [SI-LIST] Re: Digest Number 885, s s
  166. » [SI-LIST] Books/references on power/ground distribution, Chris McGrath
  167. » [SI-LIST] Fwd: Re: Digest Number 885, Michael Sachtjen
  168. » [SI-LIST] Re: Books/references on power/ground distribution, paresh . mody
  169. » [SI-LIST] Signal Integrity Secrets -- Revealed!, harry
  170. » [SI-LIST] SI opportunity, Mohammad Ali
  171. » [SI-LIST] Re: 3.125Gpbs Based backplane solutions, Rotem Gazit
  172. » [SI-LIST] 40 Gb/s serial link driver, Ed Sayre III
  173. » [SI-LIST] Re: 40 Gb/s serial link driver, Stuart Brorson
  174. » [SI-LIST] New web site for si-list related papers and documents, Raymond Anderson
  175. » [SI-LIST] Question about AC analysis for weak inversion MOS using HSPICE, Guo Yawei
  176. » [SI-LIST] Can you tell me some books or papers about class C amplifier?, Guo Yawei
  177. » [SI-LIST] SI opportunity at Dell Austin, along with other engineeringposit ions, Michael_Greim
  178. » [SI-LIST] N-port problem in interconnects, Amitava Bhaduri
  179. » [SI-LIST] Full device simulator?, Stuart Brorson
  180. » [SI-LIST] Repeaters in DSM interconnects, manthos labropoulos
  181. » [SI-LIST] PCI trace impedance, Sidney S
  182. » [SI-LIST] Question on DIMM's, Sidney S
  183. » [SI-LIST] Re: N-port problem in interconnects, Geoff Stokes
  184. » [SI-LIST] Re: Question on DIMM's, Jim_Pankratz
  185. » [SI-LIST] Re: [IS-LIST] Using Scattering Parameters with PSPICE, Clewell, Craig