Posts for si-list, 08-2009

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» [SI-LIST] Re: symmetric coupled striplines... - Lambert Simonovich
» [SI-LIST] Re: Trace width selection for high speed serial links - steve weir
» [SI-LIST] CTI >600 - costel_t
» [SI-LIST] Re: symmetric coupled striplines... - Ishwar Hosagrahar
» [SI-LIST] Re: Trace width selection for high speed serial links - wolfgang . maichen
» [SI-LIST] Re: Trace width selection for high speed serial links - Aubrey Sparkman
» [SI-LIST] Re: Trace width selection for high speed serial links - wolfgang . maichen
» [SI-LIST] Trace width selection for high speed serial links - jhasson
» [SI-LIST] Re: TDR impedance measurement and rise time - Mick zhou
» [SI-LIST] AW: Control Impedance testing - Havermann, Gert
» [SI-LIST] Re: Control Impedance testing - Istvan Novak
» [SI-LIST] Re: Advice for routing differential pair out of a BGA - Istvan Novak
» [SI-LIST] Advice for routing differential pair out of a BGA - jhasson
» [SI-LIST] Re: Control Impedance testing - steve weir
» [SI-LIST] Control Impedance testing - BO-LIAO
» [SI-LIST] Re: Shall we build a wiki site for EEE - colin_warwick
» [SI-LIST] Re: symmetric coupled striplines... - Yuriy Shlepnev
» [SI-LIST] Re: TDR impedance measurement and rise time - Istvan Novak
» [SI-LIST] Re: Power Plane resonance analysis - Istvan Novak
» [SI-LIST] symmetric coupled striplines... - Ishwar Hosagrahar
» [SI-LIST] Re: Shall we build a wiki site for EEE - Joel Brown
» [SI-LIST] Shall we build a wiki site for EEE - tubecn tubecn
» [SI-LIST] SI quiz - V S
» [SI-LIST] Re: TDR impedance measurement and rise time - Mick zhou
» [SI-LIST] Re: TDR impedance measurement and rise time - Mick zhou
» [SI-LIST] Re: Power Plane resonance analysis - Haller, Robert
» [SI-LIST] new pop quiz on bethesignal.com - Eric Bogatin
» [SI-LIST] Re: Power Plane resonance analysis - Ihsan Erdin
» [SI-LIST] Re: Power Plane resonance analysis - Ihsan Erdin
» [SI-LIST] Beginners Quiz for Signal Integrity - V S
» [SI-LIST] Re: Meaning of clock forwarding - Ria R
» [SI-LIST] Re: Power Plane resonance analysis - steve weir
» [SI-LIST] Re: Power Plane resonance analysis - Aleksandr Oysgelt
» [SI-LIST] VHDL - SIL analysis software - Manish Narayane
» [SI-LIST] Re: Power Plane resonance analysis - Istvan Novak
» [SI-LIST] Power Plane resonance analysis - Sandhya I. M.
» [SI-LIST] Re: DDR PHY - Ron Nikel
» [SI-LIST] Re: DDR PHY - Jennifer Maharani
» [SI-LIST] Regarding S-Parameter and SSN - karthik_package
» [SI-LIST] Re: DDR PHY - Michael Greim
» [SI-LIST] DDR PHY - Jennifer Maharani
» [SI-LIST] Announcing the 2009 IEEE SCV Chapter EMC Mini-Symposium: October 15-16 - Oscar Fallah
» [SI-LIST] Re: Meaning of clock forwarding - steve weir
» [SI-LIST] Re: Meaning of clock forwarding - Joseph . Schachner
» [SI-LIST] Need a better SERDES - N. Paul Taddonio
» [SI-LIST] Re: SiBeam - Ray Anderson
» [SI-LIST] Re: Meaning of clock forwarding - Michael Greim
» [SI-LIST] Meaning of clock forwarding - Ria R
» [SI-LIST] Re: PDN question - Patrick G. Andre
» [SI-LIST] Re: PDN question - Patrick G. Andre
» [SI-LIST] SiBeam - Jennifer Maharani
» [SI-LIST] PWR/GND Bus (SSN simulation) - Mohamad Haghtalab
» [SI-LIST] Re: Digital Interconnect - Alexandre Desnoyers
» [SI-LIST] SI opening - Goutham Sabavat (gsabavat)
» [SI-LIST] Re: Digital Interconnect - Jory McKinley
» [SI-LIST] Digital Interconnect - Mohamad Haghtalab
» [SI-LIST] Routing 1G diff ethernet traces - Lakshmi N. Sundararajan - PTU
» [SI-LIST] Re: Old paper - Jennifer Maharani
» [SI-LIST] Re: Old paper - Theo Markettos
» [SI-LIST] Re: PDN question - Ravinder . Ajmani
» [SI-LIST] Re: PDN question - Lynne D. Green
» [SI-LIST] Re: PDN question - Patrick G. Andre
» [SI-LIST] Re: PDN question - Daniel Paradis (paradid)
» [SI-LIST] Re: PDN question - Lynne D. Green
» [SI-LIST] Re: PDN question - Daniel Paradis (paradid)
» [SI-LIST] Re: PDN question - Rick Brooks (ricbrook)
» [SI-LIST] Re: PDN question - Lynne D. Green
» [SI-LIST] Re: PDN question - Dan Smith
» [SI-LIST] Re: PDN question - wolfgang . maichen
» [SI-LIST] Re: PDN question - steve weir
» [SI-LIST] PDN question - Joel Brown
» [SI-LIST] Re: SONNETLITE AS A PCB DESIGN TOOL? - wolfgang . maichen
» [SI-LIST] SONNETLITE AS A PCB DESIGN TOOL? - padma gundala
» [SI-LIST] Re: PCB Design tools - Craig Sullivan
» [SI-LIST] PCB Design tools - padma gundala
» [SI-LIST] Re: FEXT reduction by very small spacings - Herman Ruckerbauer
» [SI-LIST] To S-parameterize or not to S-parameterize? - colin_warwick
» [SI-LIST] Re: DDRII write problem!! - Michael Greim
» [SI-LIST] Re: DDRII write problem!! - sonlhc
» [SI-LIST] Re: DDRII write problem!! - TinaWu
» [SI-LIST] Re: DDRII write problem!! - Heyfitch
» [SI-LIST] Re: DDRII write problem!! - lee xu
» [SI-LIST] Re: DDRII write problem!! - Heyfitch
» [SI-LIST] Re: DDRII write problem!! - TinaWu
» [SI-LIST] Re: DDRII write problem!! - Chandrashekhar Kalyanaraman
» [SI-LIST] DDRII write problem!! - TinaWu
» [SI-LIST] Asian IBIS Summit (China) Second Announcement - Bob Ross
» [SI-LIST] Re: PVC material and dielectric loss - Neo
» [SI-LIST] Re: PVC material and dielectric loss - Howard Johnson
» [SI-LIST] Re: PVC material and dielectric loss - Neo
» [SI-LIST] Re: About Skin Effect - LY
» [SI-LIST] FEXT reduction by very small spacings - Eric Bogatin
» [SI-LIST] Old paper - Jennifer Maharani
» [SI-LIST] Re: PVC material and dielectric loss - Kenneth W. Egan
» [SI-LIST] PVC material and dielectric loss - Neo
» [SI-LIST] Re: FEXT reduction by very small spacings - Istvan Novak
» [SI-LIST] Re: About Skin Effect - Howard Johnson
» [SI-LIST] Re: FEXT reduction by very small spacings - Hermann Ruckerbauer
» [SI-LIST] HSPICE Simulation with S-Parameter (S2P) - See Hour
» [SI-LIST] Re: About Skin Effect - steve weir
» [SI-LIST] About Skin Effect - LY
» [SI-LIST] Re: FEXT reduction by very small spacings - Istvan Novak
» [SI-LIST] Re: FEXT reduction by very small spacings - steve weir
» [SI-LIST] Re: Gaussian Pulse - Howard Johnson
» [SI-LIST] Re: FEXT reduction by very small spacings - Hermann Ruckerbauer
» [SI-LIST] Re: FEXT reduction by very small spacings - steve weir
» [SI-LIST] FEXT reduction by very small spacings - Hermann Ruckerbauer
» [SI-LIST] Twin-ax model - Michael Rose
» [SI-LIST] Re: SPT Cable? - steve weir
» [SI-LIST] Re: SPT Cable? - Bill Grenoble
» [SI-LIST] Re: Gaussian Pulse - steve weir
» [SI-LIST] Re: SPT Cable? - steve weir
» [SI-LIST] Gaussian Pulse - Behzad
» [SI-LIST] SPT Cable? - Neo
» [SI-LIST] FPGA Camp - Aug'26 - Call For Speakers - Vikash Rungta (vrungta)
» [SI-LIST] Re: High speed serial links over copper cables - Hassan O . Ali
» [SI-LIST] Re: High speed serial links over copper cables - Neo
» [SI-LIST] SAS/PCIE Cable Material - Neo
» [SI-LIST] Need SAS 24AWG Cable model - Neo
» [SI-LIST] Re: Ibis model Request! - steve weir
» [SI-LIST] Re: Ibis model Request! - Mohamad Haghtalab
» [SI-LIST] Ibis model Request! - Mohamad Haghtalab
» [SI-LIST] An unusual use for comb generator - Doug Smith
» [SI-LIST] DesignCon 2010 Call for Papers Deadline Extended! - Yuriy Shlepnev
» [SI-LIST] Re: effect of common choke on high speed differential signals - Joel Brown
» [SI-LIST] Power Integrity Measurements - Eric Bogatin
» [SI-LIST] Re: Power Integrity Measurments - Istvan Novak
» [SI-LIST] Re: Power Integrity Measurments - steve weir
» [SI-LIST] Re: Power Integrity Measurments - on-die impedance - Cosmin Iorga
» [SI-LIST] Re: Power Integrity Measurments - Frank_Paglia
» [SI-LIST] Re: Power Integrity Measurments - olaney
» [SI-LIST] Re: Power Integrity Measurements - colin_warwick
» [SI-LIST] Power Integrity Measurments - rula . bakleh
» [SI-LIST] Test Message - Ray Anderson
» [SI-LIST] Re: Lowest cost way to implement 16 5Gbps SERDES channels - Richard Jungert
» [SI-LIST] effect of common choke on high speed differential signals - Joel Brown
» [SI-LIST] Free Webinar on IBIS Model Quality - Timothy Coyle
» [SI-LIST] AW: LossBudgetForPCIe - Havermann, Gert
» [SI-LIST] LossBudgetForPCIe - lakshmi.narayanan
» [SI-LIST] Re: Lowest cost way to implement 16 5Gbps SERDES channels - Richard Jungert
» [SI-LIST] Re: refurbished VNA - Julian Ferry
» [SI-LIST] Re: Latest Industry SAS and SATA specs. - luc . durand
» [SI-LIST] Latest Industry SAS and SATA specs. - Linda Mazaheri (lmazaher)
» [SI-LIST] Re: Two page scan PDF of fringing field conformal mapping -- Re: Re: Fringing fields of a circular disc capacitor - Jason R. Miller
» [SI-LIST] Re: refurbished VNA - Ray Anderson
» [SI-LIST] Re: Two page scan PDF of fringing field conformal mapping -- Re: Re: Fringing fields of a circular disc capacitor - Kevin G. Rhoads
» [SI-LIST] Re: refurbished VNA - colin_warwick
» [SI-LIST] Asian IBIS Summit (China) First Announcement - Bob Ross
» [SI-LIST] Re: refurbished VNA - eoin . mcgibney
» [SI-LIST] refurbished VNA - Ben Chia
» [SI-LIST] si-list back "on the air" - Ray Anderson
» [SI-LIST] differential traces referenced to a power plane in dual stripline - Michael Rose
» [SI-LIST] AW: Re: Lowest cost way to implement 16 5Gbps SERDES channels - Havermann, Gert
» [SI-LIST] Re: Lowest cost way to implement 16 5Gbps SERDES channels - N. Paul Taddonio
» [SI-LIST] Two page scan PDF of fringing field conformal mapping -- Re: Re: Fringing fields of a circular disc capacitor - Kevin G. Rhoads
» [SI-LIST] Lowest cost way to implement 16 5Gbps SERDES channels - Chris Johnson
» [SI-LIST] Re: Evaluation Boards - Yuriy Shlepnev
» [SI-LIST] Informal poll: Which of these conferences are you likely to attend? - colin_warwick
» [SI-LIST] Evaluation Boards - Mohamad Haghtalab
» [SI-LIST] Re: Free webcast from Agilent EEsof EDA: Signal Integrity Design Using Fast Channel Simulation and Eye Diagram Statistics - colin_warwick
» [SI-LIST] test post 1 - John Madden