Posts for si-list, 08-2007

Browse: Last Month: 07-2007 Main Archive Page Next Month: 09-2007

» [SI-LIST] Re: How to properly simulate signal integrity across PCBs interconnected by Flex? -
» [SI-LIST] Re: How to properly simulate signal integrity across PCBs interconnected by Flex? -
» [SI-LIST] hapice simulation of Z_tdr -
» [SI-LIST] Re: How to properly simulate signal integrity across PCBs interconnected by Flex? -
» [SI-LIST] A Hyperlynx7.7 Boardsim tutor in Santa Clara? -
» [SI-LIST] Re: FW: TDR S-parameter and correlation -
» [SI-LIST] How to properly simulate signal integrity across PCBs interconnected by Flex? -
» [SI-LIST] Re: FW: TDR S-parameter and correlation -
» [SI-LIST] Re: Cisco Systems Opportunities-San Bruno, California -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Cisco Systems Opportunities-San Bruno, California -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] Conduction cooled board -
» [SI-LIST] Re: the difference of current profile between power supply path, signal path and return path in a circuit loop -
» [SI-LIST] Re: return path -
» [SI-LIST] Re: FW: TDR S-parameter and correlation -
» [SI-LIST] Re: FW: TDR S-parameter and correlation -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] Re: FW: TDR S-parameter and correlation -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] TDR S-parameter and correlation -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Design Guide or Analysis? -
» [SI-LIST] fiber-weave effect alive and well? -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] Re: TDR S-parameter and correlation -
» [SI-LIST] TDR S-parameter and correlation -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: the difference of current profile between power supply path, signal path and return path in a circuit loop -
» [SI-LIST] Re: the difference of current profile between power supply path, signal path and return path in a circuit loop -
» [SI-LIST] the difference of current profile between power supply path, signal path and return path in a circuit loop -
» [SI-LIST] Re: split plane crossing -
» [SI-LIST] Re: split plane crossing -
» [SI-LIST] Re: split plane crossing -
» [SI-LIST] Re: split plane crossing -
» [SI-LIST] Re: split plane crossing -
» [SI-LIST] split plane crossing -
» [SI-LIST] Re: return path -
» [SI-LIST] Re: return path -
» [SI-LIST] Re: return path -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: fiber-weave effect alive and well? -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] fiber-weave effect alive and well? -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Asian IBIS Summit (China) - Agenda -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Resonant Modes -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] 2 copies of postings? -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Request example transmission line structures for 2d field solver -
» [SI-LIST] Request for example transmission line models and their 2d solver results -
» [SI-LIST] Conductor loss reduction at High Frequency -
» [SI-LIST] Re: DDR3 On-Board -
» [SI-LIST] Re: Effect of PCB trace cross-section on SI -
» [SI-LIST] Re: Effect of PCB trace cross-section on SI -
» [SI-LIST] Re: Effect of PCB trace cross-section on SI -
» [SI-LIST] Re: Conductor loss reduction at High Frequency -
» [SI-LIST] Re: DDR3 On-Board -
» [SI-LIST] Conductor loss reduction at High Frequency -
» [SI-LIST] DDR3 On-Board -
» [SI-LIST] Re: Resonant Modes -
» [SI-LIST] Re: PCIe Oscilloscope -
» [SI-LIST] Re: Resonant Modes -
» [SI-LIST] Re: Resonant Modes -
» [SI-LIST] Re: Resonant Modes -
» [SI-LIST] Re: PCIe Oscilloscope -
» [SI-LIST] Re: Effect of PCB trace cross-section on SI -
» [SI-LIST] Re: Resonant Modes -
» [SI-LIST] 答复: Resonant Modes -
» [SI-LIST] Re: PCIe Oscilloscope -
» [SI-LIST] Effect of PCB trace cross-section on SI -
» [SI-LIST] Resonant Modes -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] FW: Re: hi -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: Stripline more lossy than Microstrip? -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: Stripline more lossy than Microstrip? -
» [SI-LIST] Stripline more lossy than Microstrip? -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: hi -
» [SI-LIST] AE Position for Spice Characterization Open in San Jose and Austin. -
» [SI-LIST] Re: How to measure the resistance, inductance and capacitance parasitic of a packaged chip? -
» [SI-LIST] Re: How to measure the resistance, inductance and capac itance parasitic of a packaged chip? -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Intern Position in Andover MA. -
» [SI-LIST] Re: hi -
» [SI-LIST] How to measure the resistance, inductance and capacitance parasitic of a packaged chip? -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: software needed -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: software needed -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: hi -
» [SI-LIST] Re: software needed -
» [SI-LIST] hi -
» [SI-LIST] Re: software needed -
» [SI-LIST] Asian IBIS Summit (Japan) Fifth Announcement -
» [SI-LIST] Re: software needed -
» [SI-LIST] Re: software needed -
» [SI-LIST] Re: software needed -
» [SI-LIST] Re: software needed -
» [SI-LIST] Re: software needed -
» [SI-LIST] software needed -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Free SI training in Beijing China by IO Methodology on Sept. 10 -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Power Decoupling, again.... -
» [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance -
» [SI-LIST] signal integrity events coming up -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] FW: Re: SATA board to board connector question -
» [SI-LIST] Re: SATA board to board connector question -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: regarding the stack up -
» [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance -
» [SI-LIST] Re: regarding the stack up -
» [SI-LIST] regarding the stack up -
» [SI-LIST] Re: Memory CAS Latency (CL2 vs CL3) -
» [SI-LIST] Re: Memory CAS Latency (CL2 vs CL3) -
» [SI-LIST] Dynamic noise analysis of inverter -
» [SI-LIST] SATA board to board connector question -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Memory CAS Latency (CL2 vs CL3) -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: how tables (waveform/pullup/down etc..) in a IBIS files are used/interpeted by IBIS simulators -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] WE# asserted but data does not toggle -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Re: Undershoot issues -
» [SI-LIST] Undershoot issues -
» [SI-LIST] Re: Job Opening at 3PARData Inc -
» [SI-LIST] Re: Pull up and pull down curves in PCI local bus specifications -
» [SI-LIST] Re: Pull up and pull down curves in PCI local bus specifications -
» [SI-LIST] Power integrity post follow up -
» [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance -
» [SI-LIST] Re: diff pairs and spacing -
» [SI-LIST] Re: how tables (waveform/pullup/down etc..) in a IBIS files are used/interpeted by IBIS simulators -
» [SI-LIST] how to model the power supply current ? -
» [SI-LIST] Pull up and pull down curves in PCI local bus specifications -
» [SI-LIST] Re: diff pairs and spacing -
» [SI-LIST] Re: how tables (waveform/pullup/down etc..) in a IBIS files are used/interpeted by IBIS simulators -
» [SI-LIST] how tables (waveform/pullup/down etc..) in a IBIS files are used/interpeted by IBIS simulators -
» [SI-LIST] diff pairs and spacing -
» [SI-LIST] Ansoft Worldwide Application Workshop in Bangalore (11 September 2007) -
» [SI-LIST] Asian IBIS Summit (China) Sixth Announcement -
» [SI-LIST] Re: reflection coeficient -
» [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance -
» [SI-LIST] RF and SI Engineer wanted at Amkor -
» [SI-LIST] Re: reflection coeficient -
» [SI-LIST] Re: reflection coeficient -
» [SI-LIST] Re: Reverse Pulse Technique method? -
» [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance -
» [SI-LIST] Re: Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance -
» [SI-LIST] Decoupling of digital power i PCB's, how do we avoid pole peaks in the impedance, how far up in frequency do we need low impedance -
» [SI-LIST] SV: Separating IBIS or Spice models into single model files for ICAP/4 import (Intusoft) -
» [SI-LIST] Re: reflection coeficient -
» [SI-LIST] Re: reflection coeficient -
» [SI-LIST] Re: reflection coeficient -
» [SI-LIST] Re: reflection coeficient -
» [SI-LIST] reflection coeficient -
» [SI-LIST] Re: Reverse Pulse Technique method? -
» [SI-LIST] Re: Reverse Pulse Technique method? -
» [SI-LIST] Re: Reverse Pulse Technique method? -
» [SI-LIST] Re: Reverse Pulse Technique method? -
» [SI-LIST] Re: Reverse Pulse Technique method? -
» [SI-LIST] Reverse Pulse Technique method? -
» [SI-LIST] Re: PCB with Embedded ESD Protection -
» [SI-LIST] PCB with Embedded ESD Protection -
» [SI-LIST] Re: need help with micro probes -
» [SI-LIST] need help with micro probes -
» [SI-LIST] Re: Customer support positions at Mentor Graphics -
» [SI-LIST] Customer support positions at Mentor Graphics -
» [SI-LIST] Re: Query -
» [SI-LIST] Query -
» [SI-LIST] Join the thousands of people who got slim -
» [SI-LIST] Asian IBIS Summit (Japan) Fourth Announcement -
» [SI-LIST] Re: query -
» [SI-LIST] Re: query -
» [SI-LIST] query -
» [SI-LIST] Re: PCIe Oscilloscope -
» [SI-LIST] PCB layout free student version -
» [SI-LIST] Re: PCIe Oscilloscope -
» [SI-LIST] Re: PCIe Oscilloscope -
» [SI-LIST] Re: PCIe Oscilloscope -
» [SI-LIST] PCIe Oscilloscope -
» [SI-LIST] Boston Area EMI Workshop 8/22 -
» [SI-LIST] DDR3 Fly by topology -
» [SI-LIST] IBIS seminar in Fremont CA on Oct 4-5 -
» [SI-LIST] Asian IBIS Summit (China) Fifth Announcement -
» [SI-LIST] SSN Analysis with IBIS 4.2/AMS (was Drivers ?) -
» [SI-LIST] Re: CPU-Memory Simulation -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Separating IBIS or Spice models into single model files for ICAP/4 import (Intusoft) -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] GOOGLE - HW Leadership, Mountain View, CA -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: CPU-Memory Simulation -
» [SI-LIST] CPU-Memory Simulation -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] mobile phone emi into nearby circuits -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] GM/Buss. Dev. Mgr High Speed Interconnects -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] Re: Circle bus topology; Circular Firing Squad? -
» [SI-LIST] IBISCHK4 version 4.2.2 executables on-line! -
» [SI-LIST] R: Building a SI department -
» [SI-LIST] Re: Building a SI department -
» [SI-LIST] Re: Building a SI department -
» [SI-LIST] Building a SI department -