Posts for si-list, 08-2005

Browse: Last Month: 07-2005 Main Archive Page Next Month: 09-2005

» [SI-LIST] test -
» [SI-LIST] Re: A doubt in PADS 2005 -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] A doubt in PADS 2005 -
» [SI-LIST] Re: Question for PSPICE users -
» [SI-LIST] Re: Question for PSPICE users -
» [SI-LIST] Re: Question for PSPICE users -
» [SI-LIST] Re: Driver strength and trace capacitance -
» [SI-LIST] Re: Driver strength and trace capacitance -
» [SI-LIST] Driver strength and trace capacitance -
» [SI-LIST] Resistors at High-Frequency -
» [SI-LIST] Re: Active capacitance canceling circuitry -
» [SI-LIST] Power Beaming -
» [SI-LIST] Re: 50 Ohm vs 75 ohm -
» [SI-LIST] Re: 50 Ohm vs 75 ohm -
» [SI-LIST] 50 Ohm vs 75 ohm -
» [SI-LIST] Re: Active capacitance canceling circuitry -
» [SI-LIST] Active capacitance canceling circuitry -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] Re: VME connector models -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Question for PSPICE users -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Length matching for ZBT -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Re: Measure ESD induced noise -
» [SI-LIST] Re: Measure ESD induced noise -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Re: Measure ESD induced noise -
» [SI-LIST] current mode outputs differential pair -
» [SI-LIST] Re: Measure ESD induced noise -
» [SI-LIST] Re: Measure ESD induced noise -
» [SI-LIST] Fwd: Query -
» [SI-LIST] Re: Measure ESD induced noise -
» [SI-LIST] Re: DDR2 ODT options -
» [SI-LIST] VME connector models -
» [SI-LIST] Re: Measure ESD induced noise -
» [SI-LIST] DDR2 ODT options -
» [SI-LIST] Re: Errata list for High-Speed Digital System Design by Hall/Hall/McCall? -
» [SI-LIST] Errata list for High-Speed Digital System Design by Hall/Hall/McCall? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Measure ESD induced noise -
» [SI-LIST] Re: SSTL termination resistor power -
» [SI-LIST] Low Power devices -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] SSTL termination resistor power -
» [SI-LIST] subscribe -
» [SI-LIST] Re: For SI beginner -
» [SI-LIST] Re: For SI beginner -
» [SI-LIST] Re: For SI beginner -
» [SI-LIST] Re: For SI beginner -
» [SI-LIST] Re: For SI beginner -
» [SI-LIST] Re: Skin effect resistance in package pins for IR drop calculations -
» [SI-LIST] Re: Skin effect resistance in package pins for IR drop calculations -
» [SI-LIST] Re: Connector model using 2D/3D field solver -
» [SI-LIST] Re: Connector model using 2D/3D field solver -
» [SI-LIST] Re: Connector model using 2D/3D field solver -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: RF board Vs High speed board ... RF amplifiers -
» [SI-LIST] Re: RF board Vs High speed board -
» [SI-LIST] Re: RF board Vs High speed board -
» [SI-LIST] Re: Radiated Emissions continued -
» [SI-LIST] Re: RF board Vs High speed board -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: RF board Vs High speed board -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Skin effect resistance in package pins for IR drop calculations -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Skin effect resistance in package pins for IR drop calculations -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] RF board Vs High speed board -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] [SI-LIST]: Embedded capacitance on Flex..?? -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] MiniPCI connector Spice model /IBIS model needed -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: Accounting random jitter -
» [SI-LIST] Should the signals always return back through GND -
» [SI-LIST] Accounting random jitter -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Effective Curent Source Model -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: Connector model using 2D/3D field solver -
» [SI-LIST] Re: Fwd: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Fwd: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Re: Should the signals always return back through GND -
» [SI-LIST] Fwd: Should the signals always return back through GND -
» [SI-LIST] Should the signals always return back through GND -
» [SI-LIST] Should the signals always return back through GND -
» [SI-LIST] Re: Connector model using 2D/3D field solver -
» [SI-LIST] Re: Connector model using 2D/3D field solver -
» [SI-LIST] Connector model using 2D/3D field solver -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: Ringback measuremenr with HSPICE -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] Re: ADS usage in SI analysis -
» [SI-LIST] ADS usage in SI analysis -
» [SI-LIST] Re: GPOF codes ? -
» [SI-LIST] Re: GPOF codes ? -
» [SI-LIST] GPOF codes ? -
» [SI-LIST] unsubscribe -
» [SI-LIST] Ringback measuremenr with HSPICE -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single P rocessor -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Pro cessor -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: DDR2 ODT configuration -
» [SI-LIST] Re: Radiated Emissions continued -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: Radiated Emissions continued -
» [SI-LIST] How to use connector SPICE models Webinar -
» [SI-LIST] Radiated Emissions continued -
» [SI-LIST] Re: Radiated Emissions -
» [SI-LIST] Job Opportunity at AMD Colorado -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: Radiated Emissions -
» [SI-LIST] Re: Radiated Emissions -
» [SI-LIST] Re: driver schedule in hspice -
» [SI-LIST] Re: Radiated Emissions -
» [SI-LIST] Regarding PCI protocol analyzers -
» [SI-LIST] Re: DDR2 ODT configuration -
» [SI-LIST] driver schedule in hspice -
» [SI-LIST] Re: Radiated Emissions -
» [SI-LIST] Radiated Emissions -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Simulate 100MHz DRAMs for long term failures?!?! -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: Hi and Lo in SigWave -
» [SI-LIST] Re: Hi and Lo in SigWave -
» [SI-LIST] Hi and Lo in SigWave -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re： DDR2 ODT configuration -
» [SI-LIST] DDR2 ODT configuration -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Proc essor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Proc essor -
» [SI-LIST] Re: model selector -
» [SI-LIST] model selector -
» [SI-LIST] Re: Clock Distribution -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Pro cessor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: Clock Distribution -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: 回复： Re: hold time -
» [SI-LIST] 回复： Re: hold time -
» [SI-LIST] Re: hold time -
» [SI-LIST] hold time -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: Clock Distribution -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: Clock Distribution -
» [SI-LIST] Clock Distribution -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] Re: termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] termination for routing 8 SDRAMs to single Processor -
» [SI-LIST] SerDes Position -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: SMPS -
» [SI-LIST] Re: SMPS -
» [SI-LIST] Re: onchip interconnects, their dependence on PVT conditions -
» [SI-LIST] Re: SMPS -
» [SI-LIST] Re: SMPS -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: onchip interconnects, their dependence on PVT conditions -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: onchip interconnects, their dependence on PVT conditions -
» [SI-LIST] onchip interconnects, their dependence on PVT conditions -
» [SI-LIST] Re: SMPS -
» [SI-LIST] Re: Ground plane question -
» [SI-LIST] Re: SMPS -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Current Flow through a capacitor -
» [SI-LIST] 2006 International Symposium on EMC in Singapore -
» [SI-LIST] Re: 1-2 day contract job -- Crosstalk Survey of a PCB -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Static power consumption -
» [SI-LIST] Re: Static power consumption -
» [SI-LIST] Re: Static power consumption -
» [SI-LIST] Re: Static power consumption -
» [SI-LIST] Static power consumption -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Current Flow -
» [SI-LIST] Current Flow -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: si-list Digest V5 #307 -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] 1-2 day contract job -- Crosstalk Survey of a PCB -
» [SI-LIST] Return Path -
» [SI-LIST] Re: ESD strips on board edge -
» [SI-LIST] Re: ESD strips on board edge -
» [SI-LIST] Re: ESD strips on board edge -
» [SI-LIST] Re: Package modeling tools -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Re: Return Path -
» [SI-LIST] Return Path -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: IBIS in hpsice -
» [SI-LIST] Re: IDC connector Spice models -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] IDC connector Spice models -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: ESD strips on board edge -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Re: IBIS in hpsice -
» [SI-LIST] Re: Which layer is better for GHz signals -
» [SI-LIST] Which layer is better for GHz signals -
» [SI-LIST] Re: ESD strips on board edge -
» [SI-LIST] Re: ESD strips on board edge -
» [SI-LIST] Re: ESD strips on board edge -
» [SI-LIST] Re: IBIS in hpsice -
» [SI-LIST] Re: Package modeling tools -
» [SI-LIST] Re: Query on Fast slow and typical simulation -
» [SI-LIST] IBIS in hpsice -
» [SI-LIST] ESD strips on board edge -
» [SI-LIST] Off-spec Use of Protection Components -
» [SI-LIST] Re: Query on Fast slow and typical simulation -
» [SI-LIST] Re: Query on Fast slow and typical simulation -
» [SI-LIST] Query on Fast slow and typical simulation -
» [SI-LIST] Re: PCI Express lane to lane skew -
» [SI-LIST] C via model -- simple clarification please -
» [SI-LIST] Re: Crosstalk in time units -
» [SI-LIST] Re: Crosstalk in time units -
» [SI-LIST] Crosstalk in time units -
» [SI-LIST] hcsl specification -
» [SI-LIST] Re: 回复： Er range of FR4 -
» [SI-LIST] Re: PCI Express lane to lane skew -
» [SI-LIST] Re: PCI Express lane to lane skew -
» [SI-LIST] 回复： Er range of FR4 -
» [SI-LIST] Re: One strange question on my Hspice simulation! -
» [SI-LIST] One strange question on my Hspice simulation! -
» [SI-LIST] PCI Express lane to lane skew -
» [SI-LIST] Package modeling tools -
» [SI-LIST] Re: Ground plane question -
» [SI-LIST] Re: Ground plane question -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: Er range of FR4 -
» [SI-LIST] Re: »Ø¸´£º Re: Question on Obtaining Z parameter through VNA -
» [SI-LIST] Er range of FR4 -
» [SI-LIST] Re: »Ø¸´£º Re: Question on Obtaining Z parameter through VNA -
» [SI-LIST] Re: Ground plane question -
» [SI-LIST] Re: Ground plane question -
» [SI-LIST] Re: Ground plane question -
» [SI-LIST] Re: si-list Digest V5 #299 -
» [SI-LIST] Re: 回复： Re: Question on Obtaining Z parameter through VNA -
» [SI-LIST] Re: »Ø¸´£º Re: Question on Obtaining Z parameter through VNA -
» [SI-LIST] 回复： Re: Question on Obtaining Z parameter through VNA -
» [SI-LIST] Ground plane question -
» [SI-LIST] Thomas M Tokar/Cleveland/RA/Rockwell is out of the office. -
» [SI-LIST] Query on Pci Express insertion loss specification -
» [SI-LIST] Re: Question on Obtaining Z parameter through VNA -
» [SI-LIST] Re: Question on Obtaining Z parameter through VNA -
» [SI-LIST] Question on Obtaining Z parameter through VNA -
» [SI-LIST] Re: ??: Re: How to use Intel's model? -
» [SI-LIST] Power Integrity Special session at 2005 IEEE EMC symposium in Chicago (8/8-8/12) -
» [SI-LIST] Re: Question on ground trace in TL -
» [SI-LIST] Re: ??: Re: How to use Intel's model? -
» [SI-LIST] Re: ??: Re: How to use Intel's model? -
» [SI-LIST] Re: true differential IBIS problem -
» [SI-LIST] Asian IBIS Summit First Announcement -
» [SI-LIST] Re: ??: Re: How to use Intel's model? -
» [SI-LIST] Re: Question on ground trace in TL -
» [SI-LIST] Question on ground trace in TL -
» [SI-LIST] Thomas M Tokar/Cleveland/RA/Rockwell is out of the office. -
» [SI-LIST] true differential IBIS problem -