Posts for si-list, 06-2007

Browse: Last Month: 05-2007 Main Archive Page Next Month: 07-2007

» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Wolfgang Maichen/USW/Teradyne is out of the office. -
» [SI-LIST] Re: FW: DC-blocking transmission-line -
» [SI-LIST] Re: digital circuits radiated emission as a function of VDD -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] ATCS Field Applications Eng Position. -
» [SI-LIST] Re: digital circuits radiated emission as a function of VDD -
» [SI-LIST] Re: FW: DC-blocking transmission-line -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] Blank -
» [SI-LIST] DC-blocking transmission-line -
» [SI-LIST] Job Opening at Wipro Technologies -
» [SI-LIST] test -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] Re: FW: DC-blocking transmission-line -
» [SI-LIST] Re: 12 port model with 4 port VNA -
» [SI-LIST] Re: digital circuits radiated emission as a function of VDD -
» [SI-LIST] Re: DC-blocking transmission-line - noting a lack of hi-lites I added in response -
» [SI-LIST] Re: digital circuits radiated emission as a function of VDD -
» [SI-LIST] Re: digital circuits radiated emission as a function of VDD -
» [SI-LIST] digital circuits radiated emission as a function of VDD -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] FW: DC-blocking transmission-line -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] Re: DC-blocking transmission-line -
» [SI-LIST] DC-blocking transmission-line -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: 12 port model with 4 port VNA -
» [SI-LIST] 12 port model with 4 port VNA -
» [SI-LIST] Asian IBIS Summit (Japan) First Announcement -
» [SI-LIST] Re: DDR-400 T-topology and simulation questions -
» [SI-LIST] Re: DDR-400 T-topology and simulation questions -
» [SI-LIST] USAGE OF TIE CELLS and TIE PINS -
» [SI-LIST] Asian IBIS Summit (China) Second Announcement -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: why no class-I/II in SSTL_1.8 -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] why no class-I/II in SSTL_1.8 -
» [SI-LIST] DDR-400 T-topology and simulation questions -
» [SI-LIST] Re: step response simulators -
» [SI-LIST] step response simulators -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: Matching Differntial Pairs -
» [SI-LIST] DDR consecutive bits -
» [SI-LIST] Re: How does multiple Ghz high speed signal behave on a sheet of conductor plane? -
» [SI-LIST] Re: How does multiple Ghz high speed signal behave on a sheet of conductor plane? -
» [SI-LIST] How does multiple Ghz high speed signal behave on a sheet of conductor plane? -
» [SI-LIST] Re: attachment test -
» [SI-LIST] attachment test -
» [SI-LIST] SI Position in Austin, TX -
» [SI-LIST] Matching Differntial Pairs -
» [SI-LIST] Re: Convergence problem with DDR DRAM IBIS model -
» [SI-LIST] Re: Convergence problem with DDR DRAM IBIS model -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: Convergence problem with DDR DRAM IBIS model -
» [SI-LIST] Re: Characteristic Impedance -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: free signal integrity analysis tools -
» [SI-LIST] Convergence problem with DDR DRAM IBIS model -
» [SI-LIST] free signal integrity analysis tools -
» [SI-LIST] SI and FAE engineer openings -
» [SI-LIST] Re: SSTL_2 doubt -
» [SI-LIST] HIGH DC Current on GND Plane -
» [SI-LIST] HIGH DC Current on GND Plane -
» [SI-LIST] Re: f vs. Tf vs. jitter -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: f vs. Tf vs. jitter -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: SI Tools -
» [SI-LIST] FW: FW: Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: FW: Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: FW: Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: SSTL_2 doubt -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: f vs. Tf vs. jitter -
» [SI-LIST] FW: Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: SI Tools -
» [SI-LIST] Re: SSTL_2 doubt -
» [SI-LIST] SI Tools -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: f vs. Tf vs. jitter -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Job Opening at Spansion -
» [SI-LIST] Re: SSTL_2 doubt -
» [SI-LIST] Re: f vs. Tf vs. jitter -
» [SI-LIST] Re: passive component .vs. series component -
» [SI-LIST] Re: f vs. Tf vs. jitter -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: passive component .vs. series component -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] f vs. Tf vs. jitter -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: passive component .vs. series component -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] Re: passive component .vs. series component -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: SSTL_2 doubt -
» [SI-LIST] Re: passive component .vs. series component -
» [SI-LIST] Re: SSTL_2 doubt -
» [SI-LIST] passive component .vs. series component -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Anti-copper around BNC center conductor vs. return loss in HD input circuits. -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: HIGH DC Current on GND Plane -
» [SI-LIST] HIGH DC Current on GND Plane -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: SSTL_2 doubt -
» [SI-LIST] SSTL_2 doubt -
» [SI-LIST] Modeling conductor effects in serial data channel interconnects -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Diif pair geometry trade offs -
» [SI-LIST] Re: Resistor package - model -
» [SI-LIST] Anti-copper around BNC center conductor vs. return loss in HD input circuits. -
» [SI-LIST] Diif pair geometry trade offs -
» [SI-LIST] Re: Resistor package - model -
» [SI-LIST] Resistor package - model -
» [SI-LIST] Principal Signal Integrity Engineer -
» [SI-LIST] Diif pair geometry trade offs -
» [SI-LIST] Silicon Image Signal Integrity Job Position Opened -
» [SI-LIST] Re: Characteristic Impedance -
» [SI-LIST] Re: Characteristic Impedance -
» [SI-LIST] Re: Characteristic Impedance -
» [SI-LIST] Re: Getting started material for S-parameters for passive interconnect -
» [SI-LIST] Characteristic Impedance -
» [SI-LIST] Re: Getting started material for S-parameters for passive interconnect -
» [SI-LIST] Getting started material for S-parameters for passive interconnect -
» [SI-LIST] Re: Question about differental to common mode conversion -
» [SI-LIST] Re: Power Planes - 3.3V / 2.5 -
» [SI-LIST] Intel Intern Position Opened -
» [SI-LIST] Re: Power Planes - 3.3V / 2.5 -
» [SI-LIST] Power Planes - 3.3V / 2.5 -
» [SI-LIST] Power Plane - Split Plane -
» [SI-LIST] Join the thousands of people who got slim -
» [SI-LIST] Re: USB cable model -
» [SI-LIST] Re: USB cable model -
» [SI-LIST] Asian IBIS Summit (China) First Announcement -
» [SI-LIST] HW DIRECTOR CISCO SYSTEMS IMMEDIATE OPENING -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: soldering plastic balls -
» [SI-LIST] Re: Mil or Mils? -
» [SI-LIST] soldering plastic balls -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Flicker noise simulation -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: Mil or Mils? -
» [SI-LIST] Re: Mil or Mils? -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Mil or Mils? -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: FER Test Vs BER Test in SATA -
» [SI-LIST] Common design flaws that keep showing up in new designs -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] way off topic don't you think? -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: JTAG-EJTAG -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] JTAG-EJTAG -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: Matching within 1 mil is just plain sillyness -
» [SI-LIST] Re: Question about differential to common mode conversi on -
» [SI-LIST] Question about differental to common mode conversion -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Matching within 1 mil is just plain sillyness, IMO -
» [SI-LIST] Re: USB cable model -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] USB cable model -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] Re: matching within 1 mil -
» [SI-LIST] matching within 1 mil -
» [SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines -
» [SI-LIST] JTAG -