Posts for si-list, 06-2001

Browse: 05-2001 Main Archive Page Next Month: 07-2001

» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] PowerPCB Pads...... -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Chassis ground -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] high included message content percentage........ -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: 3D field solver -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Chassis ground -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: 3D field solver -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Chassis ground -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: si-list Digest V1 #30 -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: si-list Digest V1 #30 -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: 3D field solver -
» [SI-LIST] Re: 3D field solver -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Chassis ground -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: si-list Digest V1 #30 -
» [SI-LIST] Re: Book -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] 3D field solver -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Book - (Chassis - signal ground) -
» [SI-LIST] Re: Chassis ground -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: si-list Digest V1 #30 -
» [SI-LIST] Re: Chassis ground -
» [SI-LIST] Re: Chassis ground -
» [SI-LIST] Re: Book -
» [SI-LIST] Re: Book -
» [SI-LIST] Re: Book -
» [SI-LIST] Re: copper thickness of a ref plane -
» [SI-LIST] Book -
» [SI-LIST] Chassis ground -
» [SI-LIST] Re: copper thickness of a ref plane -
» [SI-LIST] Re: Validation of XTK results for clock skews -
» [SI-LIST] Where to advertise DSP Job ? -
» [SI-LIST] Re: Validation of XTK results for clock skews -
» [SI-LIST] Re: nRESET -
» [SI-LIST] nRESET 2 -
» [SI-LIST] nRESET -
» [SI-LIST] Re: copper thickness of a ref plane -
» [SI-LIST] Re: Hspice core dump -
» [SI-LIST] Re: copper thickness of a ref plane -
» [SI-LIST] copper thickness of a ref plane -
» [SI-LIST] Re: IBIS2XTK v. SPI2MOD -
» [SI-LIST] Re: IBIS2XTK v. SPI2MOD -
» [SI-LIST] IBIS2XTK v. SPI2MOD -
» [SI-LIST] Re: Crosstalk between different layers -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Crosstalk between different layers -
» [SI-LIST] Re: set si-list digest2 -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] set si-list digest2 -
» [SI-LIST] Re: Improve the heat on a PCB -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Hspice core dump -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Validation of XTK results for clock skews -
» [SI-LIST] New App. Note Available -
» [SI-LIST] Validation of XTK results for clock skews -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: Improve the heat on a PCB -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] FYI: Solder ... -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: Hspice core dump -
» [SI-LIST] Re: Hspice core dump -
» [SI-LIST] Hspice core dump -
» [SI-LIST] Re: Improve the heat on a PCB -
» [SI-LIST] Improve the heat on a PCB -
» [SI-LIST] measuring Hi-Z and Lo-Z state -
» [SI-LIST] Re: 1GHz clock needed, please share your info with me. -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: 1GHz clock needed, please share your info with me. -
» [SI-LIST] Re: 1GHz clock needed, please share your info with me. -
» [SI-LIST] Re: SI Position Open -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: SI Position Open READ THIS!!!! -
» [SI-LIST] Re: matching differential impedance for edge-coupled lines -
» [SI-LIST] SI Position Open -
» [SI-LIST] Re: matching differential impedance for edge-coupled lines -
» [SI-LIST] Re: matching differential impedance for edge-coupled lines -
» [SI-LIST] Re: matching differential impedance for edge-coupled lines -
» [SI-LIST] LVTTL I/O spec for 3.3V -
» [SI-LIST] matching differential impedance for edge-coupled lines -
» [SI-LIST] commands -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: measuring Hi-Z and Lo-Z state -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] measuring Hi-Z and Lo-Z state -
» [SI-LIST] Re: Voltage rating of a Ceramic capacitor -
» [SI-LIST] Voltage rating of a Ceramic capacitor -
» [SI-LIST] Re: The PCB is a component -
» [SI-LIST] Re: The PCB is a component -
» [SI-LIST] Re: The PCB is a component -
» [SI-LIST] The PCB is a component -
» [SI-LIST] Re: admin commands sent to si-list -
» [SI-LIST] Re: admin commands sent to si-list -
» [SI-LIST] Re: Seeking a coupled transmission line model -
» [SI-LIST] admin commands sent to si-list -
» [SI-LIST] Re: Seeking a coupled transmission line model -
» [SI-LIST] Re: Seeking a coupled transmission line model -
» [SI-LIST] Re: set hidden -
» [SI-LIST] Re: set hidden -
» [SI-LIST] Re: Information on CML I/O's -
» [SI-LIST] set hidden -
» [SI-LIST] "who [SI-List}" -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] who si-list -
» [SI-LIST] Seeking a coupled transmission line model -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Even/Odd mode impedance -
» [SI-LIST] Re: Even/Odd mode impedance -
» [SI-LIST] conector -
» [SI-LIST] Re: Even/Odd mode impedance -
» [SI-LIST] Re: Even/Odd mode impedance -
» [SI-LIST] Odd/Even mode impedance -
» [SI-LIST] Even/Odd mode impedance -
» [SI-LIST] Re: Looking for VHDM cable assembly solutions........ -
» [SI-LIST] Looking for VHDM cable assembly solutions........ -
» [SI-LIST] Differential signals - even and odd modes -
» [SI-LIST] Re: Measuring high speed signals -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Measuring high speed signals -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Measuring high speed signals -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Re: Ideal driver characteristics -
» [SI-LIST] Measuring high speed signals -
» [SI-LIST] Ideal driver characteristics -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Inductance of Via -
» [SI-LIST] Re: Mentor IS? -
» [SI-LIST] EPEP'2001 reminder for July 10, 2001 deadline -
» [SI-LIST] Re: Attachments to si-list being disabled -
» [SI-LIST] Re: Surface roughness of PCB tracks at track/substrate interface ? -
» [SI-LIST] Serpentine shapes -
» [SI-LIST] Re: Large attachments -
» [SI-LIST] Re: Surface roughness of PCB tracks at track/substrate interface ? -
» [SI-LIST] Re: Serpentine switchback lengths -
» [SI-LIST] K/a Adam on basic design question -
» [SI-LIST] Serpentine switchback lengths -
» [SI-LIST] Serpentine shapes -
» [SI-LIST] Surface roughness of PCB tracks at track/substrate interface ? -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Large attachments -
» [SI-LIST] Mentor IS? -
» [SI-LIST] Attachments to si-list being disabled -
» [SI-LIST] Re: : Frequency based on rise time for drivers -
» [SI-LIST] Re: : Frequency based on rise time for drivers -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: The types of drivers? -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: Information on CML I/O's -
» [SI-LIST] Information on CML I/O's -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] FW: HSPICE W element field solver model -
» [SI-LIST] The types of drivers? -
» [SI-LIST] Hello from the staff -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: more data on FR4 loss at high freq, FYI -
» [SI-LIST] Inductance of Via -
» [SI-LIST] HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] more data on FR4 loss at high freq, FYI -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: si-list @ new home -
» [SI-LIST] Re: SSTL_3 output buffer design -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] ANT-10Gig Electrical Interface -
» [SI-LIST] Re: HSPICE W element field solver model -
» [SI-LIST] SSTL_3 output buffer design -
» [SI-LIST] HSPICE W element field solver model -
» [SI-LIST] 1GHz clock needed, please share your info with me. -
» [SI-LIST] Re: : pecl termination -
» [SI-LIST] List Management Instructions -
» [SI-LIST] Re: : Asymmetric Differential Stripline -
» [SI-LIST] Re: si-list @ new home -
» [SI-LIST] si-list @ new home -
» [SI-LIST] Re: test message -
» [SI-LIST] Re: test message -
» [SI-LIST] test message -
» [SI-LIST] test 3 -
» [si-list] test #2 -
» [si-list] this is a test message -