Posts for si-list, 04-2007

Browse: Last Month: 03-2007 Main Archive Page Next Month: 05-2007

» [SI-LIST] Re: Non-Functional Pads -
» [SI-LIST] Re: SSO SSTL Vs LVTTL -
» [SI-LIST] Re: SSO SSTL Vs LVTTL -
» [SI-LIST] Re: Non-Functional Pads -
» [SI-LIST] SSO SSTL Vs LVTTL -
» [SI-LIST] Re: Spice recommendation -
» [SI-LIST] Re: Drivers ? -
» [SI-LIST] Re: Drivers ? -
» [SI-LIST] Re: TDR Analysis Equipment..Tektronix vs. Agilent? -
» [SI-LIST] Re: Non-Functional Pads -
» [SI-LIST] Non-Functional Pads -
» [SI-LIST] User interfaces -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: Spice recommendation -
» [SI-LIST] Re: Spice recommendation -
» [SI-LIST] Re: Spice recommendation -
» [SI-LIST] Re: Spice recommendation -
» [SI-LIST] Re: Spice recommendation -
» [SI-LIST] Spice recommendation -
» [SI-LIST] Re: Backplane speed -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: Drivers ? -
» [SI-LIST] Cisco Systems Internship Opportunity -
» [SI-LIST] Re: TDR Analysis Equipment..Tektronix vs. Agilent? -
» [SI-LIST] Re: TDR Analysis Equipment..Tektronix vs. Agilent? -
» [SI-LIST] Re: TDR Analysis Equipment..Tektronix vs. Agilent? -
» [SI-LIST] Re: Backplane speed -
» [SI-LIST] Re: Drivers ? -
» [SI-LIST] Backplane speed -
» [SI-LIST] Drivers ? -
» [SI-LIST] building models from TDR measurements -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: Transmission Line Causality -
» [SI-LIST] Re: Two Layer routing -
» [SI-LIST] Re: Transmission Line Causality -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: Two Layer routing -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: Transmission Line Causality -
» [SI-LIST] Two Layer routing -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Transmission Line Causality -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Transmission Line Causality -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: Memory bus datapattern -
» [SI-LIST] Two Layer Substrate packaging -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: Memory bus datapattern -
» [SI-LIST] Memory bus datapattern -
» [SI-LIST] Re: BGA Vs QFP -
» [SI-LIST] Stimulus dilemma for pwr/gnd model -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] usb2.0 eye template -
» [SI-LIST] Recall: BGA Vs QFP -
» [SI-LIST] Re: BGA Vs QFP -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: IBIS model for PCI Express Gen 2 -
» [SI-LIST] TDR Analsis Equipment..Tektronix vs Agilent? -
» [SI-LIST] Re: IBIS model for PCI Express Gen 2 -
» [SI-LIST] IBIS model for PCI Express Gen 2 -
» [SI-LIST] Re: ROHS -
» [SI-LIST] CISCO SYSTEMS -
» [SI-LIST] BGA Vs QFP -
» [SI-LIST] Re: My endpoint -
» [SI-LIST] Recent ibischk4 Version 4.2.1 Improvements -
» [SI-LIST] Re: ROHS -
» [SI-LIST] IBISCHK4 parser updated; IBIS 4.2 now an ANSI specification -
» [SI-LIST] Re: usb2.0 eye template -
» [SI-LIST] usb2.0 eye template -
» [SI-LIST] Austin Area Job Opening -
» [SI-LIST] Re: ROHS -
» [SI-LIST] Re: Bus contention between FPGA and ZBT -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: ROHS -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: ROHS -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] ROHS -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] DDR2 Pulse width -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Error running s2ibis3 software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Bus contention between FPGA and ZBT -
» [SI-LIST] Re: High Temp PCB Material -
» [SI-LIST] Re: Bus contention between FPGA and ZBT -
» [SI-LIST] Re: High Temp PCB Material -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Bus contention between FPGA and ZBT -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Re: Disadvantages of wider traces -
» [SI-LIST] Disadvantages of wider traces -
» [SI-LIST] +++ SI Expert Needed +++ -
» [SI-LIST] +++ SI Expert Needed +++ -
» [SI-LIST] Re: LVDS termination method -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Re: Low Cost PCB Layout Software -
» [SI-LIST] Low Cost PCB Layout Software -
» [SI-LIST] Re: LVDS termination method -
» [SI-LIST] Re: LVDS termination method -
» [SI-LIST] LVDS termination method -
» [SI-LIST] Bus contention between FPGA and ZBT -
» [SI-LIST] Re: Regarding differential termination -
» [SI-LIST] Re: Disadvantage of NEC2 -
» [SI-LIST] Disadvantage of NEC2 -
» [SI-LIST] RF / Microwave Design Engineer Position at Freescale Semiconductor, Tempe Arizona -
» [SI-LIST] Re: Regarding differential termination -
» [SI-LIST] Re: Regarding differential termination -
» [SI-LIST] Regarding differential termination -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Re: New Book -
» [SI-LIST] Sr. SI Engineering opportunity with Cisco -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Class in Austin, Texas -
» [SI-LIST] Re: FW: Re: Good book about jitter.... -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Bi-Directional interfaces at speeds higher than 5Gb/s -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] SMPTE RP-184 -
» [SI-LIST] Re: High Temp PCB Material -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] Re: High Temp PCB Material -
» [SI-LIST] FW: Re: Good book about jitter.... -
» [SI-LIST] Re: Good book about jitter.... -
» [SI-LIST] songful unkind -
» [SI-LIST] Re: SSO doubt -
» [SI-LIST] Re: High Temp PCB Material -
» [SI-LIST] Books for sale. -
» [SI-LIST] Re: High Temp PCB Material -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] High Temp PCB Material -
» [SI-LIST] SSO doubt -
» [SI-LIST] European IBIS Summit at DATe 2007 - Agenda & Call for Paticipation -
» [SI-LIST] Re: ADC GND Noise -
» [SI-LIST] ADC GND Noise -
» [SI-LIST] ADC GND Noise -
» [SI-LIST] ADC GND Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: Hspice to matlab -
» [SI-LIST] Re: Hspice to matlab -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: experiences with new field solvers / methods? -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] experiences with new field solvers / methods? -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: ADC Gnd Noise -
» [SI-LIST] ADC Gnd Noise -
» [SI-LIST] ADC Gnd Noise -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: Hspice to matlab -
» [SI-LIST] Re: Hspice to matlab -
» [SI-LIST] Probe card -
» [SI-LIST] Hspice to matlab -
» [SI-LIST] Re: NPU / DDR interface bug issue -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: NPU / DDR interface bug issue -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: NPU / DDR interface bug issue -
» [SI-LIST] Re: NPU / DDR interface bug issue -
» [SI-LIST] NPU / DDR interface bug issue -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Cadence Designer Network - CDNLive! SV 2007 Call for Papers -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: Extracting waveguide s-parameter on anisotropic material -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: impedance and Characteristic impedanece -
» [SI-LIST] Re: Extracting waveguide s-parameter on anisotropic material -
» [SI-LIST] Rubber Band Theory of Circuit Design -
» [SI-LIST] European IBIS Summit @ DATe 2007 - Fourth Call for Participation -
» [SI-LIST] Cisco Systems, RTP, NC, SI Intern Position -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Basic doubt -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Basic doubt -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Cisco Systems, RTP, NC, SI Intern Position -
» [SI-LIST] Job opening for SI Engr. -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Basic doubt -
» [SI-LIST] Basic doubt -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] IBIS Workshop -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-Hatched Reference Planes -
» [SI-LIST] Re: SSO doubt -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-Hatched Reference Planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Bogatin presentations now posted at BeTheSignal.com -
» [SI-LIST] SSO doubt -
» [SI-LIST] R: Extracting waveguide s-parameter on anisotropic material -
» [SI-LIST] Re: overshoot and undershoot different swing -
» [SI-LIST] Extracting waveguide s-parameter on anisotropic material -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: overshoot and undershoot different swing -
» [SI-LIST] Re: overshoot and undershoot different swing -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Re: overshoot and undershoot different swing -
» [SI-LIST] Re: overshoot and undershoot different swing -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] overshoot and undershoot different swing -
» [SI-LIST] Optimal is Looking for SI Engineers -
» [SI-LIST] Re: Cross-hatched reference planes -
» [SI-LIST] Cross-hatched reference planes -