Posts for si-list, 01-2007

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» [SI-LIST] Re: 4 Port VNA recommendations? -
» [SI-LIST] Re: PCB Trace impedance algorithms -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Agenda, IBIS Summit at DesignCon for Feb. 1, 2007 -
» [SI-LIST] Re: 4 Port VNA recommendations? -
» [SI-LIST] Re: BGA Current -
» [SI-LIST] Re: BGA Current -
» [SI-LIST] Re: BGA Current -
» [SI-LIST] PCI Express Edge Connector Models -
» [SI-LIST] Re: BGA Current -
» [SI-LIST] BGA Current -
» [SI-LIST] 4 Port VNA recommendations? -
» [SI-LIST] DDR2 - termination of UQDS -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: QLogic ISP2100 -
» [SI-LIST] Signal Integrity opening at LSI Logic -
» [SI-LIST] Re: PCB Trace impedance algorithms -
» [SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? -
» [SI-LIST] QLogic ISP2100 -
» [SI-LIST] Re: need to find a commercial Near-field Scan service in bay area -
» [SI-LIST] mEEt and gEEk SI-lister meeting reservation deadline is tomorrow! -
» [SI-LIST] Re: PCB Trace impedance algorithms -
» [SI-LIST] Re: PCB Trace impedance algorithms -
» [SI-LIST] Re: PCB Trace impedance algorithms -
» [SI-LIST] Re: PCB Trace impedance algorithms -
» [SI-LIST] PCB Trace impedance algorithms -
» [SI-LIST] Spice-related Application Engineer Position in San Jose -
» [SI-LIST] Re: How much plane under traces is required for providing return current path -
» [SI-LIST] Re: How much plane under traces is required for providing return current path -
» [SI-LIST] How much plane under traces is required for providing return current path -
» [SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] Re: IBIS creation -
» [SI-LIST] IBIS creation -
» [SI-LIST] Re: Let's talk laminate induced skew -
» [SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? -
» [SI-LIST] Re: Does anyone know how to convert IBIS version 3.2 to version 1.1? -
» [SI-LIST] Does anyone know how to convert IBIS version 3.2 to version 1.1? -
» [SI-LIST] need to find a commercial Near-field Scan service in bay area -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: S-parameter -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Let's talk laminate induced skew -
» [SI-LIST] Re: Let's talk laminate induced skew -
» [SI-LIST] Re: Let's talk laminate induced skew -
» [SI-LIST] SSTL doubts -
» [SI-LIST] SSTL_2 -
» [SI-LIST] Let's talk laminate induced skew -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Regarding the technical document archive for this forum -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Sub .100 ohm measurements -
» [SI-LIST] Re: Regarding the technical document archive for this forum -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Small DC resistance measurments -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Small DC resistance measurments -
» [SI-LIST] Re: Regarding the technical document archive for this forum -
» [SI-LIST] Re: R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Small DC resistance measurments -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Dust and humidity impact on the signal -
» [SI-LIST] Re: Small DC resistance measurments -
» [SI-LIST] Re: Question on varying the coupling ratio on a dif ferential pair -
» [SI-LIST] Small DC resistance measurments -
» [SI-LIST] R: Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] R: Dust and humidity impact on the signal -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Dust and humidity impact on the signal -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Regarding the technical document archive for this forum -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] S-parameter -
» [SI-LIST] Re: Ferrite Bead Vs. Inductor -
» [SI-LIST] Re: Interface standards -
» [SI-LIST] Re: Advanced high spped prop question -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Interface standards -
» [SI-LIST] AW: Ferrite Bead Vs. Inductor -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Ferrite Bead Vs. Inductor -
» [SI-LIST] Thanks for answering my question -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Ferrite Bead Vs. Inductor -
» [SI-LIST] Re: Ferrite Bead Vs. Inductor -
» [SI-LIST] Ferrite Bead Vs. Inductor -
» [SI-LIST] FW: Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Question on varying the coupling ratio on a differential pair -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Meet your fellow SI-listers face to face at DesignCon! -
» [SI-LIST] 4 Port VNA recommendations? -
» [SI-LIST] FW: Advanced high spped prop question -
» [SI-LIST] Advanced high spped prop question -
» [SI-LIST] Re: Low-Q Controlled-ESR Bypass Capacitors -
» [SI-LIST] Re: HSPICE w/ Verilog-AMS model of DC/DC converter (Time Domain), DesignCon material posted -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: HSPICE w/ Verilog-AMS model of DC/DC converter (Time Domain) -
» [SI-LIST] Re: Internal package aggressors/PCB routing -
» [SI-LIST] Internal package aggressors/PCB routing -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] HSPICE w/ Verilog-AMS model of DC/DC converter (Time Domain) -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: DDR Clock & Length Matchin -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] TEST -
» [SI-LIST] Re: Ethernet, USB 2.0 and DVI-I Compliance testing -
» [SI-LIST] 答复: Re: DDR Clock & Length Matching -
» [SI-LIST] Re: DDR Clock & Length Matching -
» [SI-LIST] Re: DDR Clock & Length Matching -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Hyperlynx vs Signal explorer -
» [SI-LIST] DDR Clock & Length Matching -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Ethernet, USB 2.0 and DVI-I Compliance testing -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs. Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: 回复： Re: Stimulus Patterns -
» [SI-LIST] Re: 回复： Re: Stimulus Patterns -
» [SI-LIST] Re: Guard traces and Coupled bonding conductors (as promised) -
» [SI-LIST] Guard traces and Coupled bonding conductors (as promised) -
» [SI-LIST] Re: Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: Ethernet simulation question -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Hyperlynx vs Signal Explorer -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] FW: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] Re: PCB layer stackup -
» [SI-LIST] PCB layer stackup -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Ethernet simulation question -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Ethernet simulation question -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Finding That Glitch (in your design) -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] 回复： Re: Stimulus Patterns -
» [SI-LIST] Re: OT: test 2 -
» [SI-LIST] OT: test -
» [SI-LIST] Re: [Fwd: Symantec Mail Security detected prohibited content in a message sent from your address (SYM:42320213041982824699)] -
» [SI-LIST] Ethernet simulation question -
» [SI-LIST] Re: Stimulus Patterns -
» [SI-LIST] Stimulus Patterns -
» [SI-LIST] [Fwd: Symantec Mail Security detected prohibited content in a message sent from your address (SYM:42320213041982824699)] -
» [SI-LIST] A Common Design Rule Violation -
» [SI-LIST] Join the Anatrim revolution -
» [SI-LIST] A book endorsement from Bob Ross -
» [SI-LIST] new web/podcast posted on small signal measurements in high EMI environments -
» [SI-LIST] package- Dim -
» [SI-LIST] Re: Stimulus for spice-to-IBIS -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Severe EMI and Differential Measurements -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Re: Shielding clock traces on PCB's -
» [SI-LIST] Shielding clock traces on PCB's -
» [SI-LIST] Position at Intel -
» [SI-LIST] New Opening for SI Engineer -
» [SI-LIST] Re: DDR2 Clock and DQS Lines -
» [SI-LIST] Re: DDR2 Clock and DQS Lines -
» [SI-LIST] Re: DDR2 Clock and DQS Lines -
» [SI-LIST] Re: DDR2 Clock and DQS Lines -